Title:
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Syntéza a minimalizace regulárních lineárních generátorů (Czech) |
Title:
|
Synthesis and minimization of regular linear generators (English) |
Author:
|
Pužman, Josef |
Language:
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Czech |
Journal:
|
Kybernetika |
ISSN:
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0023-5954 |
Volume:
|
3 |
Issue:
|
2 |
Year:
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1967 |
Pages:
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(127)-146 |
Summary lang:
|
English |
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Category:
|
math |
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MSC:
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03D05 |
MSC:
|
68Q45 |
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Date available:
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2009-09-24T15:47:07Z |
Last updated:
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2012-06-04 |
Stable URL:
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http://hdl.handle.net/10338.dmlcz/125056 |
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Reference:
|
[1] Elspas B.: The theory of autonomous linear sequential networks.IRE Trans. CT-6 (1959, March), 1, 45-60. |
Reference:
|
[2] Gill A.: Analysis of linear sequential circuits by confluence sets.IEEE Trans. EC-13 (1964, June), 3, 226-231. Zbl 0133.09901, MR 0175700 |
Reference:
|
[3] Green J. H., San Soucie R. L.: An error correcting encoder and decoder of high efflciency.Proc. IRE 46, 1741-1744. |
Reference:
|
[4] Gruder J. F., Perlman M.: A feedback shift-register scaler.IEEE Trans. Comm. and Electr. (1964, Nov.), 6, 745-752. |
Reference:
|
[5] Huffman D. A.: The synthesis of linear sequential coding networks.In Information Theory (ed. C. Cherry), Acad. Press, New York 1956. Zbl 0152.35702 |
Reference:
|
[6] Мишина А. П., Проскуряков И. В.: Высшая алгебра (СМБ).Наука, Москва 1965. Zbl 1225.00032 |
Reference:
|
[7] Peterson W. W.: Error-correcting codes.J. Wiley, 1961, New York (ruský překlad: Коды, исправляющие оюибки. Мир, Москва 1964). Zbl 0105.32802, MR 0121260 |
Reference:
|
[8] Roth H. H.: Linear binary shift register circuits utilizing a minimum number of mod-2 adders.IEEE Trans. IT-11 (1965, April), 2, 215-220. |
Reference:
|
[9] Sholefield P. H. R.: Shift registers generating maximal length sequences.Electr. Technology 37 (1960, Oct.), 10, 389-394. |
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